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TTEP 2010

TEST TECHNOLOGY EDUCATIONAL PROGRAM 2010

http://tab.computer.org/tttc/teg/ttep

CALL FOR TUTORIAL PROPOSALS

Overview -- Author Information -- Tutorials and Education Group

Overview

The Tutorials & Education Group (TEG) of the IEEE Computer Society Test Technology Technical Council (TTTC) organizes in 2010 a comprehensive set of Test Technology Tutorials to be held in conjunction with TTTC sponsored technical meetings. The objective of this common call is to invite submissions for tutorial proposals in order to enable selecting the best fitted tutorials for each technical meeting, as part of the annual Test Technology Educational Program (TTEP).

The tutorials accepted by the Program Committee will be included in the Test Technology Educational Program, the intent of which is to serve the test and design professionals offering fundamental education and expert knowledge in state-of-the-art test technology topics.

Participation in TTEP-organized tutorials is accredited by IEEE Computer Society. Each full day tutorial corresponds to four TTEP units (half day tutorial corresponds to two TTEP units). Upon completion of every sixteen units official accreditation in the form of the “IEEE TTTC Test Technology Certificate” is presented to the participants.

The TTEP 2010 tutorials program includes (but is not limited to) the following technical meetings:

  • Design, Automation & Test in Europe Conference (DATE’10)
  • Latin American Test Workshop (LATW’10)
  • VLSI Test Symposium (VTS’10)
  • Signal Propagation on Interconnects Workshop (SPI’10)
  • International On-Line Testing Symposium (IOLTS’10)
  • International Test Conference (ITC’10)
  • Asian Test Symposium (ATS’10)

TTEP accommodates a wide range of technical areas, from mature test topics of high interest to industrial test engineers to emerging test topics with emphasis on novelty. TTEP is soliciting new and updated tutorial proposals and the topics of interest for year 2010 TTEP Tutorials include (but are not limited to):

  • Automatic test equipment
  • Board-level testing
  • Built-In Self-Test
  • Defect oriented testing
  • Design for testability
  • DFT testers
  • Diagnosis and debug
  • Embedded core testing
  • High-speed interface testing
  • Interconnect characterization
  • Memory testing
  • Mixed-Signal/Analog testing
  • Nanometer technology testing
  • On-line and field testing
  • Performance/Delay testing
  • Power issues in testing
  • System-level testing
  • Test economics
  • Test synthesis
  • Test resource partitioning
  • Validation
  • Verification
  • Wafer testing
  • Yield optimization and test

Author Information

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All tutorial proposal submissions to TTEP 2010 are to be made electronically (in PDF format using the TTEP tutorial proposal template provided on both the TTEP main web site and the submission website) through the TTEP submissions website:

http://www.molesystems.com/welcome/tttc/TTEP/2010/loginttep.php

Deadlines and key dates:

October 5, 2009: Deadline for tutorial proposals for DATE10.
November 16, 2009: Deadline for tutorial proposals for all other TTEP10 events.
November 6, 2009: Notification of acceptance for DATE10.
February 22, 2010: Notification of acceptance for the other TTEP10 events.

Contact Information:

Dimitris Gizopoulos
TTEP Chair
University of Piraeus, Greece
T: +30 210 414 2372
F: +30 210 414 2264
E: dgizop@unipi.gr
Anand Raghunathan
TTEP Vice Chair (Organization)
Purdue University, USA
T: +1 765 494 3470
F: +1 765 494 3358
E: raghunathan@purdue.edu

Yiorgos Makris
TTEP Vice Chair (Program)
Yale University, USA,
T: +1 203-432-1203
F: +1 203-432-7481
E: yiorgos.makris@yale.edu

TTEP central web site:http://tab.computer.org/tttc/teg/ttep

TTEP submissions web site: http://www.molesystems.com/welcome/tttc/TTEP/2010/loginttep.php

Tutorials and Education Group

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Tutorials and Education Group Chair
Dimitris Gizopoulos
University of Piraeus

Vice Chair (Organization)
Anand Raghunathan
Purdue University

Vice Chair (Program)
Yiorgos Makris 
Yale University

Finance
M. Nicolaidis, TIMA Laboratory

Publicity
C. Metra, University of Bologna

Planning
V. Agrawal, Auburn University
G. Robinson

Industry Relations
R. Aitken, ARM

New Topics
B. Courtois, CMP
M. Hsiao, Virginia Tech.

Audio/Visual
A. Jas, Intel

Electronic Media
S. Di Carlo, Poli. di Torino
G. Di Natale, LIRMM

Organizing Liaisons
TBD

Program Committee
TBD

For more information, visit us on the web at: http://tab.computer.org/tttc/teg/ttep

The Test Technology Educational Program 2010 (TTEP 2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel.
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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